1. Field of the Invention
The present invention relates to a novel method of making a junction gate field effect transistor (hereinafter referred to as J-FET).
More particularly, the present invention relates to a self-alignment method of making a J-FET intended to obtain a short gate length (Lg) and hence a good high frequency characteristic with a low noise performance.
2. Prior Art
Hitherto, J-FET has been generally constructed as shown in FIG. 1, wherein formings of gate PN junction and forming of source and drain ohmic regions are made in separate steps by using different masks.
When a J-FET is used for a high frequency amplification or for a low noise amplification, in general, such characteristics as a small input capacitance and high mutual conductance (g.sub.m) are required. In order to improve such characteristics, as fundamental factors in design of the J-FET, it is important to shorten the gate length Lg and to reduce the series resistance by shortening source-gate distance as much as possible. However, with the structure as shown in FIG. 1, it is necessary to use a first mask for use to make a gate region 1, and a second mask for use to make a drain region 2 and a source region 3, and registration of these two masks determines the limit of shortening the gate length and the source-gate distance, and hence determines the limit of the characteristics. In FIG. 1, numeral 4 designates a p-type silicon substrate which also works as a substrate side gate, numeral 5 designates an n-type silicon epitaxial layer and numeral 6 designates an SiO.sub.2 film. Electrodes are omitted in the drawing. Even though adopting an available most advanced technique of mass-production wherein the gate is worked to 2 .mu.m, the minimum sizes are gate length Lg of 2 .mu.m and the source-drain distance of 8 .mu.m.
As an improvement of a III-V crystal heterostructure FET for obtaining a short gate length, an invention of the U.S. Pat. No. 4,075,652, the United Kingdom Pat. No. 1,507,701, the Canadian Pat. No. 1023480 and German Pat. No. 2517049 has been proposed. But the proposed invention is not very suitable for making a J-FET of a short gate length, since it is difficult to make a selective diffusion on the III-V compound and hence the diffused gate region can not be formed and the gate electrode is on the elevated level. Therefore electrode connection to the gate has a problem of liability of cut-off and furthermore the gate is formed on the same side of the wafer as drain and source, and hence the electrode pattern on the wafer is congested thereby limiting the shortening of the drain-source distance.